Dynamic Reconfigurable CNN Accelerator for Embedded Edge Computing: A Hardware-Software Co-Design Approach to Minimize Power and Resource Consumption

Abstract

With the growing demand for efficient Convolutional Neural Network (CNN) deployments in low-power, edge computing environments, FPGAs have emerged as an ideal platform due to their parallel processing, low power consumption, and dynamic reconfiguration capabilities. This paper presents the design and implementation of a dynamic reconfigurable CNN accelerator tailored for embedded edge devices. The proposed accelerator architecture is designed with hardware-software co-design principles, optimizing for modularity and flexibility. Experimental results demonstrate significant reductions in power consumption (42.06%) and hardware resource utilization (17.76% for FF, 32.82% for LUT, 48.70% for BRAM, and 47.01% for DSP) when compared to static circuit accelerators. These improvements highlight the potential of the accelerator for a broad range of CNN applications, particularly in resource-constrained environments. Future work will focus on further optimization and extending the architecture to support CNN-based lightweight object detection algorithms.